DATE is pleased to present a special hybrid format for its 2022 event, as the situation related to COVID-19 is improving but safety measures and restrictions will remain uncertain for the upcoming months across Europe and worldwide. In transition towards a future post-pandemic event again, DATE 2022 will host a two-day live event in presence in the city of Antwerp (just north of Brussels in Belgium), to bring the community together again, followed by other activities carried out entirely online in the subsequent days. This setup combines the in-presence experience with the opportunities of on-line activities, fostering the networking and social interactions around an interesting program of selected talks and panels on emerging topics to complement the traditional DATE high-quality scientific, technical and educational activities.

DATE 2021 Awards

Awards Ceremony during DATE 2021 Closing Session

Best IP Award

AXPIKE: INSTRUCTION-LEVEL INJECTION AND EVALUATION OF APPROXIMATE COMPUTING

Isaías Bittencourt Felzmann1, João Fabrício Filho2 and Lucas Wanner2

1University of Campinas, BR; 2Unicamp/UTFPR, BR; 2Unicamp, BR

ACM SIGDA/CEDA/EDAA PhD Forum Best Poster Prize

ROBUST AND ENERGY-EFFICIENT DEEP LEARNING SYSTEMS

Muhammad Abdullah Hanif

Institute of Computer Engineering, Vienna University of Technology, AT

EXPLOITING ERROR RESILIENCE OF ITERATIVE AND ACCUMULATION BASED ALGORITHMS FOR HARDWARE EFFICIENCY

Dr. G.A. Gillani

University of Twente, NL

EDAA Outstanding Dissertations Award 2020

Topic 1:

Thesis: "Accelerator Architectures for Deep learning and Graph Processing"

Linghao Song, Ph.D. (Duke University, US, Advisor: Prof. Yiran Chen and Prof. Hai Li)

Topic 2:

Thesis: "Data Structures and Algorithms for Logic Synthesis in Advanced Technologies".

Eleonora Testa, Ph.D. (EPFL, CH; Advisors: Prof. Giovanni de Micheli and Dr. Mathias Soeken)

Topic 3:

Thesis: "Remote Attacks on FPGA Hardware"

Dennis Gnad, PhD. (KIT, DE; Advisor: Prof. Mehdi Tahoori)

Topic 4:

Thesis: "Improving DRAM Performance, Security and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins"

Jeremie Kim, Ph.D. (Carnegie Mellon University, US; Advisor: Prof. Onur Mutlu)

Previous recipients of the award

Will be announced in Closing Ceremony on Thursday, 4 February 2021

Best University Booth Award

MELODI: A MASS E-LEARNING SYSTEM FOR DESIGN, TEST, AND PROTOTYPING OF DIGITAL HARDWARE

Daniel Hauer, Friedrich Bauer, Felix Braun, Axel Jantsch, Markus D. Kobelrausch, Martin Mosbeck, Nima TaheriNejad and Philipp-Sebastian Vogt

TU Wien, AT

Awards Ceremony during DATE 2021 Opening Session

EDAA Achievement Award

Georges Gielen, KU Leuven, BE

Press release

DATE Fellow Award

Giorgio Di Natale, TIMA / Université Grenoble Alpes, FR

IEEE Fellow Award

Mehdi Tahoori, Karlsruhe Institute of Technology, DE

For contributions to resilient nanoscale integrated circuits

DATE Best Paper Awards 2021

Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the best papers. The selection is performed by the award committee composed of the Track Chairs Ian O'Connor, Theocharis Theocharides, Ilia Polian and Valeria Bertacco and the following members: Lorena Anghel, David Atienza, Koen Bertels, Christos-Savvas Bouganis, Luca Carloni, Stefano Di Carlo, Jose Flich, Pierre-Emmanuel Gaillardon, Tsung-Yi Ho, Artur Jutman, Huichu Liu, Jan Madsen, Maria K. Michael, Francesco Regazzoni, Johanna Sepulveda, Muhammad Shafique, Haralampos Stratigopoulos, Lionel Torres, Jiang Xu, Chengmo Yang.

The DATE 2021 best papers are:

D Track

Leveraging Processor Modeling and Verification for General Hardware Modules

Yue Xing, Huaxi Lu, Aarti Gupta, Sharad Malik

Princeton University

A Track

A GPU-accelerated Deep Stereo-LiDAR Fusion for Real-time High-precision Dense Depth Sensing

Haitao Meng, Chonghao Zho, Jianfeng Gu, Gang Chen

Sun Yat-sen University

T Track

Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core

Nils Wistoff1, Moritz Schneider1, Frank Gurkaynak1, Luca Benini2, Gernot Heiser3

1 ETH Zurich, 2 Università di Bologna and ETH Zurich, 3 UNSW and Data61, CSIRO

E Track

Adaptive Design of Real-Time Control Systems subject to Sporadic Overruns

Paolo Pazzaglia1, Arne Hamann2, Dirk Ziegenbein2, Martina Maggio3

1 Universität des Saarlandes, 2 Robert Bosch GmbH, 3 Lund University

 

Best Paper Award Nominations

D Track

Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design

Qi Sun1, Tinghuan Chen1, Siting Liu1, Jin Miao2, Jianli Chen3, Hao Yu4, Bei Yu1

1 The Chinese University of Hong Kong, 2 Cadence Design Systems, 3 Fudan University, 4 Southern University of Science and Technology

Leveraging Processor Modeling and Verification for General Hardware Modules

Yue Xing, Huaxi Lu, Aarti Gupta, Sharad Malik

Princeton University

3D Heterogeneous ReRAM Architecture for Training Graph Neural Networks

Aqeeb Iqbal Arkal1, Biresh Kumar Joardar1, Jana Doppa1,

Partha Pratim Pande1, Krishnendu Chakrabarty2

1 Washington State University, 2 Duke University

LSP: Collective Cross-Page Prefetching for NVM

Haiyang Pan, Yuhang Liu, Tianyue Lu, Mingyu Chen

Chinese Academy of Sciences

Efficient Resource Management of Clustered Multi-Processor Systems Through Formal Property Exploration

Ourania Spantidi1, Iraklis Anagnostopoulos1, Georgios Fainekos2

1 Southern Illinois University Carbondale, 2 Arizona State University

Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance

Sebastian Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Christian Hakert, Katharina Morik, Rodion Novkin, Lukas Pfahler, Mikail Yayla

Technical University of Dortmund

FPGA Architectures for Approximate Dense SLAM Computing

Maria-Rafaela Gkeka, Alexandros Patras, Christos D. Antonopoulos, Spyros Lalis, Nikolaos Bellas

University of Thessaly

Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure

Ravi Ledalla, Chaobo Li, Debjit Sinha, Adil Bhanji, Gregory Schaeffer, Hemlata Gupta, Jennifer Basile

IBM Corporation

COMPACT: Flow-Based Computing on Nanoscale Crossbars with Minimal Semiperimeter

Sven Thijssen1, Sumit Kumar Jha2, Rickard Ewetz1

1 University of Central Florida, 2 University of Texas at San Antonio

In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories

Arman Kazemi1, Mohammad Mehdi Sharifi1, Ann Franchesca Laguna1, Franz Mueller2, Ramin Rajaei1, Ricardo Olivo2, Thomas Kaempfe2, Michael Niemier1, X. Sharon Hu1

1 University of Notre Dame, 2 Fraunhofer IPMS-CNT

A Track

Origin: Enabling On-Device Intelligence for Human Activity Recognition Using Energy Harvesting Wireless Sensor Networks

Cyan Subhra Mishra, John (Jack) Sampson, Mahmut Kandemir, Vijaykrishnan Narayanan

The Pennsylvania State University

A GPU-accelerated Deep Stereo-LiDAR Fusion for Real-time High-precision Dense Depth Sensing

Haitao Meng, Chonghao Zho, Jianfeng Gu, Gang Chen

Sun Yat-sen University

Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache

Anurag Agarwal, Jaspinder Kaur, Shirshendu Das

Indian Institute of Technology Ropar

As Accurate as Needed, as Efficient as Possible: Approximations in DD-based Quantum Circuit Simulation

Stefan Hillmich1, Richard Kueng1, Igor L. Markov2, Robert Willie1

1 Johannes Kepler University Linz, 2 University of Michigan

T Track

Characterization and Fault Modeling of Intermediate State Defect in STT-MRAMs

Lizhou Wu1, Siddharth Rao2, Mottaqiallah Taouil1, Erik Jan Marinissen2, Gouri Sankar Kar2, Said Hamdioui1

1 Delft University of Technology, 2 IMEC

Device- and Temperature Dependency of Systematic Fault Injection Results in Artix-7 and iCE40 FPGAs

Christian Fibich1, Martin Horauer1, Roman Obermaisser2

1 University of Applied Sciences Technikum Wien, 2 University of Siegen

DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On-Chip Weight Memories in Deep Neural Network Hardware Architectures

Muhammad Abdullah Hanif1, Muhammad Shafique2

1 Vienna University of Technology, 2 New York University Abu Dhabi

Digital test of ZigBee transmitters: Validation in industrial test environment

Thibault Vayssade1, Florence Azais1, Laurent Latorre1, François Lefevre2

1 Université de Montpellier, 2 NXP Semiconductors

Making Obfuscated PUFs Secure Against Power Side-Channel Based Modeling Attacks

Trevor Kroeger1, Wei Cheng2, Sylvain Guilley2, Jean-Luc Danger2, Naghmeh Karimi1

1 University of Maryland, 2 Institut Polytechnique de Paris

Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core

Nils Wistoff1, Moritz Schneider1, Frank Gurkaynak1, Luca Benini2, Gernot Heiser3

1 ETH Zurich, 2 Università di Bologna and ETH Zurich, 3 UNSW and Data61, CSIRO

E Track

TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN Accelerators

Geng Yuan1, Payman Benham2, Yuxuan Cai1, Ali Shafiee3, Jingyan Fu4, Zhiheng Liao4, Zhengang Li1, Xiaolong Ma1, Jieren Deng5, Jinhui Wang6, Mahdi Bojnordi2, Yanzhi Wang1, Caiwen Ding5

1 Northeastern University, 2 University of Utah, 3 Samsung, 4 North Dakota State University, 5 University of Connecticut, 6 University of South Alabama

Adaptive Design of Real-Time Control Systems subject to Sporadic Overruns

Paolo Pazzaglia1, Arne Hamann2, Dirk Ziegenbein2, Martina Maggio3

1 Universität des Saarlandes, 2 Robert Bosch GmbH, 3 Lund University

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