As design complexity increases with 3DICs and time-to-market becomes a critical component in the automotive, wearables and IoT segments, reducing design cycle time while maintaining accuracy of analysis has become all the more important. To address this, a system level co-design approach in step with multi-physics analysis is presented. To mitigate errors due to manual exchange of data between various engineering teams spread across chip, package and board with design and analysis adding further level of exchange, a design flow incorporating simplification at the layout level is shown. The flow enables various levels of simplified models to be used, wherein data transfer between the complex 3D structures in layout to the thermal analysis tool is automated. The efficacy of the model simplification is verified through a test case showing comparable results for the simplified and full models.

Nowadays, design of EDA applications are not only focused on hardware/software parts and need team collaborations. In many cases as in mechatronic, powertrain and control systems, the environment has to be used with the design itself at different level of abstraction. Altair is providing environments which help users to design these multi-physics environments and interact with dedicated solvers. Cloud solutions and data analytics can also be combined to handle best design tuning for powerful multi-physics simulations.

Virtually every discussion on business trends talks about digitalization—whether it's the digital thread, digital twin, the digital enterprise, or the digitalization of everything. The goal is to harness the power of the exponential to integrate data in unprecedented ways to deliver new value and performance. As a result, the next generation of SoCs will be driven by business workloads and energy efficiencies, where software performance will define semiconductor success.

That is why a digital twin is becoming a necessity to virtually verify and validate the system performance of SoCs both pre-silicon and then throughout the lifecycle of the SoC. Thomas Heurung, technical director Europe for Siemens EDA, will explain how the digital twin is helping to drive Tera-scale IC and application systems. First by accelerating design creation of custom accelerators.Then, by supporting the shift-left in SoC verification, leading to true system validation from IP to software to systems. And ultimately the digital twin enables a digitalization of the SoC environment both pre-silicon and throughout the lifecycle of the IC.

Are you interested in learning more about the why, how (and what) of publishing a book? Publishing a book is a powerful tool, allowing you to communicate your ideas to a global audience, building your reputation in the field and accelerating your career. Join this upcoming webinar to hear from Springer Nature Editorial Director, Charles Glaser, about the stages in the publishing process and how Springer have helped many authors just like you, publish a book.  Q&A will follow to answer all your book publishing questions.

The SoC industry has seen the fast-growing and diversified demands for a wide range of RISC-V based products: from tiny low-power MCUs for consumer devices, to chips powering enterprise-grade products and datacenter servers; from one power-efficient core to a thousand GHz+ cores working cohesively. To serve the market, Andes has developed a rich portfolio of AndesCore processor IPs already used in the above scenarios. They include compact single-issue cores to feature-rich Linux-capable superscalar cores, cacheless single cores to cache-coherence multicores, and cores capable of processing floating-point and DSP data to those crunching a large volume of vector data. Based on the solid foundation, Andes continues to enrich our product offerings for higher performance efficiency as well as more flexible configurations.

In this talk, we will first give an overview of Andes existing V5 RISC-V processor lineup and present examples of how V5 processors are used in SoC. Then, we will introduce V5 IPs newly added to Andes processor portfolio, the associated software support and their performance data. We will provide an update of Andes Custom Extension™ (ACE) and show how it can further accelerate control and data paths in applications.

SoC design starts by design assembly connecting IP blocks which is just the beginning of the integration process. The difficult part is reaching the best possible PPA (Power, Performance, Area) combination within tight deadlines, while keeping engineering costs under control. In the conventional EDA (Electronic Design Automation) design flow, each task (power consumption, architecture, testing, etc.) is performed separately by an ultra-specialized team of engineers and significant design time is lost in iteration loops. The number of iterations has a great impact on the cost and time frame of the whole project.

This presentation will illustrate how to start SoC Build process much earlier compared to traditional design flows. Using a joint API handling a variety of design domains and design formats including RTL, constraints, power, physical, test, etc. Such API allows non design experts to take important design.

Also, a new dimension of design extraction is presented with a focus on “Power SoC Integration”. It is shown how the design reuse ratio is augmented by keeping engineering cost reasonably low.

The role of test is expanding from its traditional role into one that includes managing the entire silicon lifecycle. To ensure that ICs work safely and as expected throughout their operational life, the industry needs to expand from production test to a model that includes ongoing monitoring for defects, degradations, bugs, attacks, and use case surprises.

Tiny Machine Learning (TinyML) is a growing, widely popular community focusing on the deployment of Deep Learning (DL) models on microcontrollers (MCUs). To run a trained DL model on an MCU, developers must have the necessary skills to handcraft network topologies and associated hyperparameters to fit a wide range of hardware requirements including operating frequency, embedded SRAM and embedded Flash memory along with the corresponding power consumption requirements.

Unfortunately, a hand-crafted design methodology poses multiple challenges: 1) AI and embedded developers exhibit different orthogonal skills, which do not meet each other during the development of AI applications until their validation in an operational environment 2) Tools for automated network design often assume virtually unlimited resources (typically deep networks are trained on cloud- or GPU-based systems) 3) The time-to-market from conception to realization of an AI system is usually quite long. Consequently, mass market adoption of AI technologies at the deep edge is jeopardized.

Our solution is based on Sequential Model Based Optimization (SMBO) – aka Bayesian Optimization (BO) – that is the standard methodology for Automated Machine Learning (AutoML) and Neural Architecture Search (NAS). Although AutoML and NAS are successfully applied on large GPU/Cloud platforms (i.e., some AutoML/NAS tools are commercialized by Google, Amazon and Microsoft), their application is still an issue in the case of tiny devices, such as MCUs. Our approach, instead, includes “deployability” constraints – related to the hardware resources of the MCUs – into the hyperparameter optimization process, leading to this new “AutoTinyML” perspective.

This talk will present our approach, along with its pros and cons with respect to multi-objective optimization (usually adopted to reduce resource usage on cloud). A set of relevant results will be presented and discussed, providing an overview of the next open challenges and perspectives in the AutoTinyML field.