SoC design starts by design assembly connecting IP blocks which is just the beginning of the integration process. The difficult part is reaching the best possible PPA (Power, Performance, Area) combination within tight deadlines, while keeping engineering costs under control. In the conventional EDA (Electronic Design Automation) design flow, each task (power consumption, architecture, testing, etc.) is performed separately by an ultra-specialized team of engineers and significant design time is lost in iteration loops. The number of iterations has a great impact on the cost and time frame of the whole project.

This presentation will illustrate how to start SoC Build process much earlier compared to traditional design flows. Using a joint API handling a variety of design domains and design formats including RTL, constraints, power, physical, test, etc. Such API allows non design experts to take important design.

Also, a new dimension of design extraction is presented with a focus on “Power SoC Integration”. It is shown how the design reuse ratio is augmented by keeping engineering cost reasonably low.