Aim of the workshop

Automotive electronics is becoming more and more relevant in the daily life, especially with the advent of the autonomous driving. People will become 100% dependent on the proper operation of the electronic systems. The Automotive Reliability and Test workshop in Europe (ARTe or ART in Europe) intends to focus exclusively on test and reliability of automotive electronics, including IC design, test development, system-level integration, production testing, in-field test, diagnosis and repair solutions, as well as architectures and methods for reliable and safe operation in the field.

Given the success of the first five editions in the US, we would like to celebrate the ART anniversary with an extraordinary edition to be held in Europe. The ARTe Workshop wants to offer a forum for industry specialists and academic researchers to present and discuss these challenges and emerging solutions. For this first edition in the frame of the DATE conference, special focus will be given on Design-for-Test solutions.

For further information, please visit the workshop website: http://cas.polito.it/ARTe2021/

Technical program

Morning sessions

8:30-8:40 CET

Opening of the first “Automotive Test and Reliability Workshop in Europe 2021”

General Chairs:

Yervant Zorian – Synopsys, USA

Paolo Bernardi – Politecnico di Torino, Italy

Program Chairs:

Wim Dobbelaere – ON Semiconductor, Belgium

Riccardo Cantoro – Politecnico di Torino, Italy

 

8:40-9:40 CET

Technical session: “Fault detection, grading, and monitoring techniques”

Moderator: to be announced

1.A: “Automatic and Scalable Implementation Flow of Performance Monitors for Automotive MCU Using Functional Path Ring Oscillators”

Authors:

Tobias Kilian – Infineon Technologies (DE), Technical University of Munich (DE)

Heiko Ahrens, Daniel Tille, Martin Huch – Infineon Technologies (DE)

Ulf Schlichtmann – Technical University of Munich (DE)

Abstract:

The automotive industry requires high dependability for a microcontroller (MCU). Therefore, MCU manufacturers seek a precise performance screening. This paper presents an automated and scalable method for the creation of functional path ring oscillators. The implementation flow is presented accompanying the development of a new MCU.

1.B: “Low-Cost Error-Detection Mechanisms for Multi-Core Real-Time Systems”

Authors:

Gennaro S. Rodrigues, Fernanda L. Kastensmidt – Universidade Federal do Rio Grande do Sul (UFRGS), Brasil

Alberto Bosio – Ecole Centrale de Lyon, Lyon Institute of Nanotechnology, France

Vincent Pouget – IES, University of Montpellier, CNRS, France

Abstract:

This paper presents an approximate error detection technique developed for multi-core embedded systems. The proposed technique exploits approximate computing to reduce memory footprint. The proposed technique can provide redundancy-based error detection with lower costs than a traditional Duplication With Comparison (DWC). In addition, a smaller memory footprint has shown improvements in reliability. The technique is implemented on a dual-core ARM processor and evaluated under both laser fault injection. Results show that we can improve the error detection of DWC at lower cost in terms of memory footprint.

1.C: “Claiming Coverage Credit for ATPG Setup using Functional Fault Grading”

Authors:

Lee Harrison, Michael Wittke – Mentor, a Siemens Business, USA

Abstract:

For the extremely high quality requirements needed for automotive IC’s, there is a large amount of effort put into the architecting of a DFT solution for these devices, to keep the inserted test logic down to an absolute minimum and making sure that any test logic inserted into the design is as testable as possible. However regardless of how much effort is applied there are always faults within the design that are not testable with DFT test structures. Using functional fault grading technology in the context of structural test we can evaluate any faults in the design that are inherently caught by the setup of the design to run structural test, but are not actually accounted for in the running of those tests. In essence accounting for coverage of faults already covered without the need for additional patterns.

1.D: “Unique Challenges and Effectiveness of Voltage-Stressing for Activating Latent Metal-Bridging Defects in Automotive Reliability”

Authors:

W PAN, Lieyi Sheng – ON Semiconductor, USA

Zdenek Axman, Vilem Bucek – ON Semiconductor, Czech Republic

Abstract:

Overall, we have demonstrated for the first time that a well implemented V-stress scheme is very effective in activating and screening latent inter-metal defects, despite their highly irregular and variable electrical characteristics.

 

10:00-11:00 CET

Technical session: “Test quality and Reliability in Automotive”

Moderator: to be announced

2.A: “PPM Targets of Different Markets with Focus on Automotive Market”

Author:

Ralf Arnold – Infineon Technologies, Germany

Abstract:

Quality is defined as the quotient of All Counted Customer Rejects divided by the number of All Delivered Devices and is measured in PPM’s (Parts per Million). Today automotive customers request Zero PPM quality. The reason for this quality target is based on the complexity of the cars. In today’s medium-class cars there are easily 50-60 Microcontroller Units (MCUs) implemented in various applications from engine management, braking, radar, powertrain control, transmission up to autonomous driving and many more other applications. This paper describes the result of a questionnaire from ETS and ITC 2019 where the PPM targets of different markets are shown. The main focus is set on the High Automotive Quality.

2.B: “From space to automotive: early detection of burnin rejects on SiC products using a new statistical screening approach”

Authors:

Santi Alessandrino, Santina Bevilacqua – STMicroelectronics, Italy

Aurore Archimbaud, François Bergeret – ippon innovation, France

Abstract:

Quality and reliability are more and more important in automotive industry as the number of components per car increases and will increase dramatically in the next years with the electrical and autonomous vehicles. This is especially true when new technologies are going to be deployed to address power and other challenges, especially the Silicon Carbide (SiC). To support high quality standards, we have developed a new statistical multivariate method called Good Average Testing (GAT), which is an efficient tool for screening outliers, i.e. reliability issues. It is already in use for space industry and we have adapted it to the context of automotive. We propose to show is efficiency on SiC products.

2.C: “Improving IO Timing Characterization and Test Quality for Automotive Devices”

Authors:

Ben Niewenhuis, Krishna Panda, Devanathan VR, Mike Hayenga, Jason Wicker, Anthony Hill – Texas Instruments Inc., USA

Abstract:

With increasing IO interfaces in automotive SOCs, test and silicon characterization of the IO interfaces is critical to ensure strict requirements on quality and reliability. In this paper, we present silicon characterization and test quality improvements on IO interfaces with results from production automotive SOCs.

2.D: “Test Methodology Enhancements using Visual Inspection Pattern Analysis”

Authors:

Nektar Xama, Jhon Gomez, Georges Gielen – KU Leuven, Belgium

Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette – ON Semiconductor, Belgium

Abstract:

As automotive testing requirements continue to become more stringent and considering the new demands in terms of functional safety, novel viewpoints and additional sources of information are investigated to guarantee and improve automotive IC reliability. Using visual inspection information from wafers obtained between different process steps opens new possibilities to improve testing methodologies. The data can lead to more efficient and directed test development, as well as open up new ways to detect defects that threaten reliability.

 

Afternoon sessions

15:00-15:45 CET

Keynote: "More Compute Performance under the Hood: New Applications and Complexity Challenges for Automotive Microcontrollers"

Speaker: Dr. Christian Pacha – Infineon Technologies, Germany

Moderator: Paolo Bernardi – Politecnico di Torino, Italy

Abstract:

Modern automotive microcontroller are evolving towards heterogeneous SoCs with an increasing HW-SW complexity. The traditional engineering paradigms of high quality and safety requirements are combined with enhanced computational functionalities, high bandwidth communication interfaces, advanced signal processing capabilities and multi-level memory hierarchies. Market driver behind this evolution is the transformation process in the automotive industry, notably hybrid and full electric vehicles, advanced driver assistance systems and autonomous driving as well as new electrical/electronic car architectures.

This talk gives an overview how the diversifying application landscapes motivate new SoC integration paradigms. We will illustrate their impact on SoC architecture and design based on example of Infineon’s Aurix family. Typical dependencies across the development value chain ranging from the initial conceptual phase to post-Silicon, such as power-performance and thermal integrity, will be presented and analyzed considering generic industry trends in scaled microelectronics.

15:45-16:45 CET

Panel “Automotive Test and Reliability: How could IEEE1687.2 change our future?”

Moderator: Wim Dobbelaere – ON Semiconductor, Belgium

Panelists:

Stephen Sunter – Mentor, a Siemens Business, Canada

Vladimir Zivkovic – Infineon Technologies, Germany

Mark Hutner – Teradyne, USA

Hans-Martin Von Staudt – Dialog Semiconductor, Germany

Georges Gielen – University of Leuven, Belgium

Davide Appello – STMicrolectronics, Italy

 

17:00-17:45 CET

Embedded Tutorial: “Memory Testing for Automotive Applications beyond plain Test Quality”

Speaker: Dr. Martin Keim – Mentor, a Siemens Business, USA

Moderator: Elena-Ioana Vatajelu – Grenoble INP, TIMA, CNRS, France

Abstract:

Everyone understands that automotive applications demand the highest test quality. This is true for logic testing as well as for memory testing. But the story does not end with just high quality tests. In fact, quality is just one of many critical aspects implementing memory testing for such applications. In this short embedded tutorial, we will touch on several such aspects, including Memory BIST IP design and qualification, EDA tool requirements, algorithm selection and qualification, test application and repair, design and system interaction, all the way to diagnosis of field returns. 

 

17:45-18:45 CET

Panel: “New automotive design methodologies for catching latent defects and detecting anomalies online”

Moderator: Haralampos-G. Stratigopoulos – Sorbonne Universités, CNRS, LIP6, France

Panelists:

Fei Su – Intel, USA

Anthony Coyette – ON Semiconductor, Belgium

Chen He – NXP, USA

Eric Faehn – StMicroelectronics, France

Daniel Tille – Infineon Technologies, Germany

Abstract:

 The ever-increasing number of ICs deployed in a modern vehicle, combined with the increasing number of safety-related and autonomous driving features, call for more comprehensive test methods to reach sub-ppm defect escape levels. This requires also dealing with latent defects that manifest themselves after post-manufacturing test in the field of operation and are due to usage time, aging, or are triggered under specific operating conditions. This requires modeling and testing for latent defects to screen out chips with hidden reliability hazards at post-manufacturing test time, but also on-chip mechanisms for on-line concurrent detection, and possibly healing, of operation anomalies due to latent defects with the aim to expand safety features. The panel gathers five experts in the field to exchange views and discuss available solutions, trends, and open challenges.

 

18:45-19:45 CET

Closing of the first “Automotive Test and Reliability Workshop in Europe 2021”

General Chairs:

Yervant Zorian – Synopsys, USA

Paolo Bernardi – Politecnico di Torino, Italy

Program Chairs:

Wim Dobbelaere – ON Semiconductor, Belgium

Riccardo Cantoro – Politecnico di Torino, Italy