Welcome to the DATE 2021 Website

Call for Papers

Scope of the Event

The 25th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors as well as specialists in hardware and software design, test and manufacturing of electronic circuits and systems. DATE puts strong emphasis on both technology and systems, covering ICs/SoCs, emerging technologies, embedded systems and embedded software.

Structure of the Event

The multi-day event consists of a conference with regular papers, panels, hot-topic sessions, tutorials, workshops, special focus days and executives. The scientific conference is complemented by various commercial showcases presenting the state-of-the-art in design and test tools, methodologies, IP and design services, reconfigurable and other hardware platforms, embedded software and (industrial) design experiences from different application domains, such as automotive, wireless, telecom and multimedia applications. The event will host the young people programme, the university fair and multi-partner projects dissemination on innovative research activities fostering the networking and the exchange of information on relevant issues, recent research outcomes and career opportunities.

More details are available on the DATE website: www.date-conference.com.

Areas of Interest

Within the scope of the conference, the main areas of interest are: design automation, design tools and hardware architectures for electronic and embedded systems; test and dependability at system, chip, circuit and device level for analogue and digital electronics; modelling, analysis, design and deployment of embedded software and cyber-physical systems; application design and industrial design experiences.

Topics of interest include, but are not restricted to:

• System Specification and Modelling
• System-level Design Methodologies and High-Level Synthesis
• System Simulation and Validation
• Formal Methods and Verification
• Design and Test for Analogue and Mixed-Signal Circuits and Systems, and MEMS
• Design and Test of Secure Systems
• Network on Chip and Communication-Centric Design
• Architectural and Microarchitectural Design
• Low-power, Energy-efficient and Thermal-aware Design
• Approximate Computing
• Reconfigurable Systems
• Logical and Physical Analysis and Design
• Emerging Design Technologies for Future Computing
• Emerging Design Technologies for Future Memories
• Power-efficient and Sustainable Computing
• Robotics and Industry 4.0
• Automotive Systems and Smart Energy Systems
• Augmented Living and Personalized Healthcare
• Secure Systems, Circuits and Architectures
• Self-adaptive and Learning Systems
• Applications of Emerging Technologies
• Modelling and Mitigation of Defects, Faults, Variability and Reliability
• Test Generation, Test Architectures, Design for Test, and Diagnosis
• Microarchitecture-Level Dependability
• System-Level Dependability
• Real-time and Dependable Systems
• Embedded Systems for Deep Learning
• Model-based Design, Verification and Security for Embedded Systems
• Embedded Software Architectures, Compilers and Tool Chains
• Cyber-Physical Systems Design

DATE 2022 will host for the third year a two-day initiative on Autonomous Systems Design: Fueled by the progress of artificial intelligence, autonomous systems become more and more integral parts of many Internet-of-Things (IoT) and Cyber-Physical Systems (CPS) applications, such as automated driving, robotics, avionics and industrial automation. Autonomous systems are self-governed and self-adaptive systems that are designed to operate in an open and evolving environment that has not been completely defined at design time. This poses a unique challenge to the design and verification of dependable autonomous systems. The DATE Initiative on Autonomous Systems Design will include peer-reviewed papers, invited contributions and interactive sessions addressing these challenges.

Submission of Papers

All papers must be registered by Sunday, 12 September 2021 AoE (title, abstract and co-authors), the final version of the paper to be submitted by Sunday, 19 September 2021 AoE (firm deadline) via: https://www.date-conference.com/

Papers can be submitted either for standard oral presentation or for interactive presentation.

The Program Committee also encourages proposals for Special Sessions, Tutorials, Friday Workshops, University Booth Demonstrations, PhD Forum and Exhibition Theatre.

Following the last-minute transformation of DATE 2020 to a virtual conference, DATE planned to gather its community again in Grenoble, France for DATE 2021 from 1 to 5 February 2021. Again, considering the continued erratic development of the worldwide COVID-19 pandemic and thus related restrictions of world-wide travelling as well as the safety and health of the DATE community, the Organising Committees decided to also host DATE 2021 as a virtual conference.

DATE combines the world’s favourite electronic systems design and test conference with an international exhibition for electronic design, automation and test, from system-level hardware and software implementation right down to integrated circuit design. This year, the conference was held as a virtual live conference from 1 to 5 February 2021 which offered an exciting, wide-ranging technical programme.

The 2021 DATE week was opened by six in-depth technical tutorials on the main topics and given by leading experts in their respective fields. The topics covered Industrial Control Systems Security, Software-Defined Hardware: Digital Design in the 21st Century with Chisel, How Emerging Memory Technology Will Reshape Future Computing, Security in the Post-Quantum Era: Threats and Countermeasures, Automation goes both ways: ML for security and security for ML as well as CAD for SoC Security.

With the Opening Ceremony, live online on Tuesday morning, virtual DATE 2021 officially opened its doors and started off with one of the plenary keynote lectures given by John Martinis, professor of Physics at UC Santa Barbara, who gave an insight on “Quantum Supremacy Using A Programmable Superconducting Processor”.

Anna Grassellino, recently named “Woman of the Year” by the Italian magazine “D La Repubblica”, opened the afternoon live slot of the online conference with her plenary keynote lecture on “Superconducting Quantum Materials and Systems (SQMS) – a new DOE National Quantum Information Science Research Center”.

61 technical sessions were organized in line with the main conference programme, which participants could follow live during two time slots each from Tuesday to Thursday.

Awards Ceremony during DATE 2021 Closing Session

Best IP Award

AXPIKE: INSTRUCTION-LEVEL INJECTION AND EVALUATION OF APPROXIMATE COMPUTING

Isaías Bittencourt Felzmann¹, João Fabrício Filho² and Lucas Wanner²

¹University of Campinas, BR; ²Unicamp/UTFPR, BR; ²Unicamp, BR

ACM SIGDA/CEDA/EDAA PhD Forum Best Poster Prize

ROBUST AND ENERGY-EFFICIENT DEEP LEARNING SYSTEMS

Muhammad Abdullah Hanif

Institute of Computer Engineering, Vienna University of Technology, AT

EXPLOITING ERROR RESILIENCE OF ITERATIVE AND ACCUMULATION BASED ALGORITHMS FOR HARDWARE EFFICIENCY

Dr. G.A. Gillani

University of Twente, NL

EDAA Outstanding Dissertations Award 2020

Topic 1:

Thesis: "Accelerator Architectures for Deep learning and Graph Processing"

Linghao Song, Ph.D. (Duke University, US, Advisor: Prof. Yiran Chen and Prof. Hai Li)

Topic 2:

Thesis: "Data Structures and Algorithms for Logic Synthesis in Advanced Technologies".

Eleonora Testa, Ph.D. (EPFL, CH; Advisors: Prof. Giovanni de Micheli and Dr. Mathias Soeken)

Topic 3:

Thesis: "Remote Attacks on FPGA Hardware"

Dennis Gnad, PhD. (KIT, DE; Advisor: Prof. Mehdi Tahoori)

Topic 4:

Thesis: "Improving DRAM Performance, Security and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins"

Jeremie Kim, Ph.D. (Carnegie Mellon University, US; Advisor: Prof. Onur Mutlu)

Previous recipients of the award

Will be announced in Closing Ceremony on Thursday, 4 February 2021

Best University Booth Award

MELODI: A MASS E-LEARNING SYSTEM FOR DESIGN, TEST, AND PROTOTYPING OF DIGITAL HARDWARE

Daniel Hauer, Friedrich Bauer, Felix Braun, Axel Jantsch, Markus D. Kobelrausch, Martin Mosbeck, Nima TaheriNejad and Philipp-Sebastian Vogt

TU Wien, AT

Awards Ceremony during DATE 2021 Opening Session

EDAA Achievement Award

Georges Gielen, KU Leuven, BE

Press release

DATE Fellow Award

Giorgio Di Natale, TIMA / Université Grenoble Alpes, FR

IEEE Fellow Award

Mehdi Tahoori, Karlsruhe Institute of Technology, DE

For contributions to resilient nanoscale integrated circuits

DATE Best Paper Awards 2021

Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the best papers. The selection is performed by the award committee composed of the Track Chairs Ian O'Connor, Theocharis Theocharides, Ilia Polian and Valeria Bertacco and the following members: Lorena Anghel, David Atienza, Koen Bertels, Christos-Savvas Bouganis, Luca Carloni, Stefano Di Carlo, Jose Flich, Pierre-Emmanuel Gaillardon, Tsung-Yi Ho, Artur Jutman, Huichu Liu, Jan Madsen, Maria K. Michael, Francesco Regazzoni, Johanna Sepulveda, Muhammad Shafique, Haralampos Stratigopoulos, Lionel Torres, Jiang Xu, Chengmo Yang.

The DATE 2021 best papers are:

D Track

Leveraging Processor Modeling and Verification for General Hardware Modules

Yue Xing, Huaxi Lu, Aarti Gupta, Sharad Malik

Princeton University

A Track

A GPU-accelerated Deep Stereo-LiDAR Fusion for Real-time High-precision Dense Depth Sensing

Haitao Meng, Chonghao Zho, Jianfeng Gu, Gang Chen

Sun Yat-sen University

T Track

Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core

Nils Wistoff¹, Moritz Schneider¹, Frank Gurkaynak¹, Luca Benini², Gernot Heiser³

¹ ETH Zurich, ² Università di Bologna and ETH Zurich, ³ UNSW and Data61, CSIRO

E Track

Adaptive Design of Real-Time Control Systems subject to Sporadic Overruns

Paolo Pazzaglia¹, Arne Hamann², Dirk Ziegenbein², Martina Maggio³

¹ Universität des Saarlandes, ² Robert Bosch GmbH, ³ Lund University

Best Paper Award Nominations

D Track

Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design

Qi Sun¹, Tinghuan Chen¹, Siting Liu¹, Jin Miao², Jianli Chen³, Hao Yu⁴, Bei Yu¹

¹ The Chinese University of Hong Kong, ² Cadence Design Systems, ³ Fudan University, ⁴ Southern University of Science and Technology

Leveraging Processor Modeling and Verification for General Hardware Modules

Yue Xing, Huaxi Lu, Aarti Gupta, Sharad Malik

Princeton University

3D Heterogeneous ReRAM Architecture for Training Graph Neural Networks

Aqeeb Iqbal Arkal¹, Biresh Kumar Joardar¹, Jana Doppa¹,

Partha Pratim Pande¹, Krishnendu Chakrabarty²

¹ Washington State University, ² Duke University

LSP: Collective Cross-Page Prefetching for NVM

Haiyang Pan, Yuhang Liu, Tianyue Lu, Mingyu Chen

Chinese Academy of Sciences

Efficient Resource Management of Clustered Multi-Processor Systems Through Formal Property Exploration

Ourania Spantidi¹, Iraklis Anagnostopoulos¹, Georgios Fainekos²

¹ Southern Illinois University Carbondale, ² Arizona State University

Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance

Sebastian Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Christian Hakert, Katharina Morik, Rodion Novkin, Lukas Pfahler, Mikail Yayla

Technical University of Dortmund

FPGA Architectures for Approximate Dense SLAM Computing

Maria-Rafaela Gkeka, Alexandros Patras, Christos D. Antonopoulos, Spyros Lalis, Nikolaos Bellas

University of Thessaly

Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure

Ravi Ledalla, Chaobo Li, Debjit Sinha, Adil Bhanji, Gregory Schaeffer, Hemlata Gupta, Jennifer Basile

IBM Corporation

COMPACT: Flow-Based Computing on Nanoscale Crossbars with Minimal Semiperimeter

Sven Thijssen¹, Sumit Kumar Jha², Rickard Ewetz¹

¹ University of Central Florida, ² University of Texas at San Antonio

In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories

Arman Kazemi¹, Mohammad Mehdi Sharifi¹, Ann Franchesca Laguna¹, Franz Mueller², Ramin Rajaei¹, Ricardo Olivo², Thomas Kaempfe², Michael Niemier¹, X. Sharon Hu¹

¹ University of Notre Dame, ² Fraunhofer IPMS-CNT

A Track

Origin: Enabling On-Device Intelligence for Human Activity Recognition Using Energy Harvesting Wireless Sensor Networks

Cyan Subhra Mishra, John (Jack) Sampson, Mahmut Kandemir, Vijaykrishnan Narayanan

The Pennsylvania State University

A GPU-accelerated Deep Stereo-LiDAR Fusion for Real-time High-precision Dense Depth Sensing

Haitao Meng, Chonghao Zho, Jianfeng Gu, Gang Chen

Sun Yat-sen University

Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache

Anurag Agarwal, Jaspinder Kaur, Shirshendu Das

Indian Institute of Technology Ropar

As Accurate as Needed, as Efficient as Possible: Approximations in DD-based Quantum Circuit Simulation

Stefan Hillmich¹, Richard Kueng¹, Igor L. Markov², Robert Willie¹

¹ Johannes Kepler University Linz, ² University of Michigan

T Track

Characterization and Fault Modeling of Intermediate State Defect in STT-MRAMs

Lizhou Wu¹, Siddharth Rao², Mottaqiallah Taouil¹, Erik Jan Marinissen², Gouri Sankar Kar², Said Hamdioui¹

¹ Delft University of Technology, ² IMEC

Device- and Temperature Dependency of Systematic Fault Injection Results in Artix-7 and iCE40 FPGAs

Christian Fibich¹, Martin Horauer¹, Roman Obermaisser²

¹ University of Applied Sciences Technikum Wien, ² University of Siegen

DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On-Chip Weight Memories in Deep Neural Network Hardware Architectures

Muhammad Abdullah Hanif¹, Muhammad Shafique²

¹ Vienna University of Technology, ² New York University Abu Dhabi

Digital test of ZigBee transmitters: Validation in industrial test environment

Thibault Vayssade¹, Florence Azais¹, Laurent Latorre¹, François Lefevre²

¹ Université de Montpellier, ² NXP Semiconductors

Making Obfuscated PUFs Secure Against Power Side-Channel Based Modeling Attacks

Trevor Kroeger¹, Wei Cheng², Sylvain Guilley², Jean-Luc Danger², Naghmeh Karimi¹

¹ University of Maryland, ² Institut Polytechnique de Paris

Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core

Nils Wistoff¹, Moritz Schneider¹, Frank Gurkaynak¹, Luca Benini², Gernot Heiser³

¹ ETH Zurich, ² Università di Bologna and ETH Zurich, ³ UNSW and Data61, CSIRO

E Track

TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN Accelerators

Geng Yuan¹, Payman Benham², Yuxuan Cai¹, Ali Shafiee³, Jingyan Fu⁴, Zhiheng Liao⁴, Zhengang Li¹, Xiaolong Ma¹, Jieren Deng⁵, Jinhui Wang⁶, Mahdi Bojnordi², Yanzhi Wang¹, Caiwen Ding⁵

¹ Northeastern University, ² University of Utah, ³ Samsung, ⁴ North Dakota State University, ⁵ University of Connecticut, ⁶ University of South Alabama

Adaptive Design of Real-Time Control Systems subject to Sporadic Overruns

Paolo Pazzaglia¹, Arne Hamann², Dirk Ziegenbein², Martina Maggio³

¹ Universität des Saarlandes, ² Robert Bosch GmbH, ³ Lund University

DATE 2021 Proceedings are available

• 2021 (for registered attendees of the main conference)

All DATE Proceedings will also be publicly available two years after DATE! Meanwhile you will find current proceedings at IEEE Xplore Digital Library or ACM Digital Library!

The publicly available proceedings are here:

• 2019
• 2018
• 2017
• 2016
• 2015
• 1998 - 2014